Xilinx Vivado seems to think that this is synthesizable since Vivado 2017.3. Opinions anyone? (SV code, TCL, and Vivado logs at http://svn.clifford.at/handicraft/2018/vivadohier ….)pic.twitter.com/MgpgP76B7g
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The ability to use hierarchical signal naming is handy when writing test benches and doing debugging, but when writing production code it's essential to respect module ports in order to keep code from turning into hopeless spaghetti.
This is not about code you write. This is just about code the code generator produces for the IP core it generates.
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If the target code will *never* need to be read by a human then you may have an argument in favor. In that case though, why even bother with hierarchy? Just load it all into on flat module.
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This is about a specific code generator and that's just not what it does. It creates many modules that form a hierarchy and then uses hierarchical references between them. It's not my generator. I can't just make it output a flat module.
End of conversation
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