Xilinx Vivado seems to think that this is synthesizable since Vivado 2017.3. Opinions anyone? (SV code, TCL, and Vivado logs at http://svn.clifford.at/handicraft/2018/vivadohier ….)pic.twitter.com/MgpgP76B7g
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I suppose a third option, "Only if enabled via a configuration setting," is not possible in an easy way.
I'm not sure if I understand what you are suggesting. If you can run the generator in a way that avoids using this feature, why would you ever want to run it configured so that it generates less portable HDL code?
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I personally wouldn't ever (and voted accordingly), but as my discussion with whitequark illustrates, there may be others who might want such a feature.
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I was just speculating that if the cost to support it is low, it might be worth gating it behind a feature flag. But I wouldn't bother if the cost is too high.
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