Xilinx Vivado seems to think that this is synthesizable since Vivado 2017.3. Opinions anyone? (SV code, TCL, and Vivado logs at http://svn.clifford.at/handicraft/2018/vivadohier ….)pic.twitter.com/MgpgP76B7g
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Is that even part of the synthesizable subset of SV? If not, then Vivado should not allow it. Otherwise, I'd say, like others have, that it's handy but definitely very bad coding practice except for cases such as fault injection or debugging.
There is no "synthesizable subset" for SystemVerilog. There was a standard (IEEE 1364.1) that defined the synthesizable subset of Verilog (IEEE 1364). But no such standard exists for SystemVerilog (IEEE 1800). So nobody knows what is to be expected to work in SV synthesis..
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Oh dear. Well, I appreciate their optimism. ;)
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