Xilinx Vivado seems to think that this is synthesizable since Vivado 2017.3. Opinions anyone? (SV code, TCL, and Vivado logs at http://svn.clifford.at/handicraft/2018/vivadohier ….)pic.twitter.com/MgpgP76B7g
Show this thread
A little bit of context: Should a (System)Verilog code generator (I don't want to name the specific one in question) generate code like the example above when generating synthesizable HDL code?
-
-
I suppose a third option, "Only if enabled via a configuration setting," is not possible in an easy way.
-
I'm not sure if I understand what you are suggesting. If you can run the generator in a way that avoids using this feature, why would you ever want to run it configured so that it generates less portable HDL code?
- Show replies
New conversation -
-
-
The ability to use hierarchical signal naming is handy when writing test benches and doing debugging, but when writing production code it's essential to respect module ports in order to keep code from turning into hopeless spaghetti.
-
This is not about code you write. This is just about code the code generator produces for the IP core it generates.
- Show replies
New conversation -
-
-
I'd say no, it should not generate code like that, but... more for reasons of sane code style than being synthesizable. Even code generators should have some respect for vaguely reasonable code style.
Thanks. Twitter will use this to make your timeline better. UndoUndo
-
-
-
hell, no! Allowing synth tools boundry optimizations (with adding/removing ports) is one thing... But this...
Thanks. Twitter will use this to make your timeline better. UndoUndo
-
-
-
If it's a proprietary core gen, then it's not obfuscated enough. If it's an open source core gen, I'd expect meaningful identifiers and internal documentation--much like AutoFPGA provides.
Thanks. Twitter will use this to make your timeline better. UndoUndo
-
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.