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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 16 Oct 2018
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      I have just released Yosys 0.8https://github.com/YosysHQ/yosys/releases/tag/yosys-0.8 …

      2 replies 30 retweets 100 likes
    2. jospicant‏ @JoseFdo_ 16 Oct 2018
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      Replying to @oe1cxw

      Is it better for triestate?

      1 reply 0 retweets 0 likes
    3. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 17 Oct 2018
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      Replying to @JoseFdo_

      Depends on the flow

      1 reply 0 retweets 0 likes
    4. jospicant‏ @JoseFdo_ 18 Oct 2018
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      Replying to @oe1cxw

      I don’t understand. What do you refer “on the flow”? It support for example: assign a=(sel)? x:1’bz; a is on a output port.

      1 reply 0 retweets 0 likes
    5. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 18 Oct 2018
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      Replying to @JoseFdo_

      What flow are you using? What architecture are you trargeting? iCE40? ECP5? Xilinx 7-series? Or is it an ASIC flow? Or a formal verification flow? The answer is a different one for each flow.

      2 replies 0 retweets 0 likes
    6. jospicant‏ @JoseFdo_ 18 Oct 2018
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      Replying to @oe1cxw

      Ice40 on icestudio tool.

      1 reply 0 retweets 0 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 18 Oct 2018
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      Replying to @JoseFdo_

      Most of the issues with tristate outputs on iCE40 are packing/pnr issues, not Yosys issues. I think nextpnr should do a better job here than arachne-pnr. Not sure if nextpnr-ice40 is already available in icestudio. cc @JesusArroyo89

      1:14 AM - 18 Oct 2018
      1 reply 0 retweets 0 likes
        1. jospicant‏ @JoseFdo_ 18 Oct 2018
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          Replying to @oe1cxw @JesusArroyo89

          Thanks a lot.

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