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Yes, you can. Generically estimating max size is difficult. As a rule of thumb, designing for an FPGA is about 100x less area efficient than designing for an ASIC. So the expectation would be that one can emulate a 1mm x 1mm FPGA on a 1cm x 1cm FPGA on same technology node.
Or imagine this. Put 100s or 1000s blockits in a grid. Most of them would be small boolean logic function (e.g. a nor gate) or a flip-flop, but a few could also have special purposes such as being an oscillator, ADC or even a whole CPU.
Between each block you then place a multiplexer so that each block can receive its input from one of several different outputs. So even if the blocks themselves are fixed, you can build different functions by changing the multiplexers to control the flow of signals
The gap is 40x according to Zuma https://ieeexplore.ieee.org/document/6239797 …
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