As of this week I'm now officially the vice-chair of the RISC-V Bitmanipulation Task Group within the RISC-V Foundation.
Many thanks to the people who made this possible. I am very excited about this opportunity. 
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One question - is there carryless multiply anywhere in all this? ARM and x86 both have it. I can't see any mention in the main ISA doc or in this.
I am trying to coordinate with the crypto extension people on this. My current thinking is that it would be a better fit there, but we will see. I fully agree that clmul should have a spot somewhere in the ISA.
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Update: The crypto extension will likely be using vektor operations only. So my current thinking is to have scalar clmul/clmulh in the B extension and vector versions of those ops in the crypto extension.
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I hope they test that approach with popular libraries. I know many will be VL=1 as typical open source codes are not designed for parallel crypto. e.g. a web server needs many streams for parallel crypto to work, but the popular APIs (OpenSSL) are typically single stream based.
End of conversation
New conversation -
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