Hot take: The proper Verilog template for synchronously reset flip-flops looks like this. always @(posedge clk) begin [non-reset code here] if (reset) begin [reset code here] end end
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What's wrong with splitting the code over two processes; one with and the second without reset?
Less flexible, which hurts if you want to optimize for a small number of bits with reset. (In case of bitvectors you might even want to reset only some bits.) Nothing you couldn't do with two processes of course, but you'd need to make larger code changes.
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Now I don't do Verilog, In VHDL I would tackle the 'some bits reset only' by using an array of std_logic in stead of a std_log_vector or perhaps a record mixing std_logic and std_logic_vector. There must be (System)Verilog equivalents?
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There are. It's actually pretty easy to do. But still easier is the idiom I suggested in the OP.
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