Hot take: The proper Verilog template for synchronously reset flip-flops looks like this. always @(posedge clk) begin [non-reset code here] if (reset) begin [reset code here] end end
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Oh dear, I think you're right, but not "foo <= 42" I think: "reg foo = 0; always @(...) begin foo <= 42; foo <= foo; end" So the 2nd assignment gets 0, not 42?
Yes. That's putting `foo <= 42;` followed by `foo <= 0;` on the queue. They are then executed in that order, effectively assigning 0 to foo.
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It all makes sense now, thank you. My example would work under reset, but fail outside of reset. Hah! :P And since I avoid blocking statements in @(posedge clk) (due to synthesis warnings about unused regs), then your first idiom seems to be the only way.
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