Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

Hot take: The proper Verilog template for synchronously reset flip-flops looks like this. always @(posedge clk) begin [non-reset code here] if (reset) begin [reset code here] end end

Yes, and alternately: always @(posedge clock) begin [non-reset code] foo <= (reset == 1'b1) ? [reset value] : foo; bar <= (reset == 1'b1) ? [reset value] : bar; end Why? Compact, and simulates correctly if reset is X or Z. Else reset code fails to apply with an if.

Your foo and bar are stuck at the reset value because non-blocking assignment. (All non-blocking assignment to foo/bar in [non-reset code] will be ignored and blocking assignments are not allowed because you must not mix blocking and non-blocking assignments for the same reg.)

Which is to say I agree: the way I wrote it makes it easy to mix blocking and non-blocking statements, which while not forbidden AFAIK, is really asking for trouble.