Hot take: The proper Verilog template for synchronously reset flip-flops looks like this. always @(posedge clk) begin [non-reset code here] if (reset) begin [reset code here] end end
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Which is to say I agree: the way I wrote it makes it easy to mix blocking and non-blocking statements, which while not forbidden AFAIK, is really asking for trouble.
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Thanks. Not suprised. I meant that mixing separate blocking/non-blocking statements, not on the same variable, isn't forbidden, but a bad idea anyway. (I need to re-read the LRM apparently...)
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Jfyi, IEEE 1364.1 is the synthesis standard. IEEE 1364 is the LRM.
End of conversation
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