Hot take: The proper Verilog template for synchronously reset flip-flops looks like this. always @(posedge clk) begin [non-reset code here] if (reset) begin [reset code here] end end
-
If reset is not asserted, won't those lines devolve to "foo <= foo", which has no effect (except adding a delta cycle to the simulation)? I don't know what the LRM says, but wouldn't a subsequent n-b assignment override a blocking one?
If you have for example `foo <= 42; foo <= foo;` then the RHS of the second assignment refers to the value of `foo` before the first assignment. So the 2nd assignment reverts the effect of `foo <= 42;`. `x <= cond ? y : x;` is *not* identical to `if (cond) x <= y;`
-
-
Oh dear, I think you're right, but not "foo <= 42" I think: "reg foo = 0; always @(...) begin foo <= 42; foo <= foo; end" So the 2nd assignment gets 0, not 42?
-
Yes. That's putting `foo <= 42;` followed by `foo <= 0;` on the queue. They are then executed in that order, effectively assigning 0 to foo.
- Show replies
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.