Hot take: The proper Verilog template for synchronously reset flip-flops looks like this. always @(posedge clk) begin [non-reset code here] if (reset) begin [reset code here] end end
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Yes, and alternately: always @(posedge clock) begin [non-reset code] foo <= (reset == 1'b1) ? [reset value] : foo; bar <= (reset == 1'b1) ? [reset value] : bar; end Why? Compact, and simulates correctly if reset is X or Z. Else reset code fails to apply with an if.
Your foo and bar are stuck at the reset value because non-blocking assignment. (All non-blocking assignment to foo/bar in [non-reset code] will be ignored and blocking assignments are not allowed because you must not mix blocking and non-blocking assignments for the same reg.)
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If reset is not asserted, won't those lines devolve to "foo <= foo", which has no effect (except adding a delta cycle to the simulation)? I don't know what the LRM says, but wouldn't a subsequent n-b assignment override a blocking one?
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If you have for example `foo <= 42; foo <= foo;` then the RHS of the second assignment refers to the value of `foo` before the first assignment. So the 2nd assignment reverts the effect of `foo <= 42;`. `x <= cond ? y : x;` is *not* identical to `if (cond) x <= y;`
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Which is to say I agree: the way I wrote it makes it easy to mix blocking and non-blocking statements, which while not forbidden AFAIK, is really asking for trouble.
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