Hot take: The proper Verilog template for synchronously reset flip-flops looks like this. always @(posedge clk) begin [non-reset code here] if (reset) begin [reset code here] end end
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always @(posedge clk) begin if (reset) begin [reset code here] end else begin [non-reset code here] end end seems more correct right? Both would synthesize identical
Only if you do assign reset values to *all* registers written to in [reset code]. If you have some registers in that block that do not have a reset value then your code will infer additional logic and they are not identical. That's the whole point.
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not having assignments in a dataflow language would be asking too much but everything must be C computing science, the area when nothing is ever learned
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Well i finally synthesised the two forms of coding for signal that doesnt need reset. You are spot on , the synthesis was different for both coding styles. Thanks for sharing!!
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