Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

always @(posedge clk) begin if (reset) begin [reset code here] end else begin [non-reset code here] end end seems more correct right? Both would synthesize identical

Only if you do assign reset values to *all* registers written to in [reset code]. If you have some registers in that block that do not have a reset value then your code will infer additional logic and they are not identical. That's the whole point.

I use patterns like this in programming since it’s more explicit about scope and less needlessly verbose, ie: x = 1 if y > 5: x = 2 Rather than: if y > 5: x = 2 else: x = 1

When the 'if' condition es met then you have two 'write" operations with your preferred idiom, instead of one with the other. Wouldn't this escalate with larger code, making your option less optimal?

Yes, and alternately: always @(posedge clock) begin [non-reset code] foo <= (reset == 1'b1) ? [reset value] : foo; bar <= (reset == 1'b1) ? [reset value] : bar; end Why? Compact, and simulates correctly if reset is X or Z. Else reset code fails to apply with an if.

Your foo and bar are stuck at the reset value because non-blocking assignment. (All non-blocking assignment to foo/bar in [non-reset code] will be ignored and blocking assignments are not allowed because you must not mix blocking and non-blocking assignments for the same reg.)

Didn't @OlofKindgren write a blog article about using resets in this fashion recently? I know I personally like to split my always blocks up and then use cascaded ifs to handle resets, but this is still a nice trick with a more general application.

Right here: https://olofkindgren.blogspot.com/2017/11/resetting-reset-handling.html … "Last assignment wins" is such a useful idiom.