We are helping a subcontractor hire a Verilog person (with a strong focus on Verilog language details and being able to work with the Verilog LRM). So I created a short Quiz for them to use. Anyone here brave enough to try it? My DMs are open.
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I just looked at this, it's diabolical! I'm going to have to cosy up to the Verilog spec and dive into sign extension, x pessimism, and other dark corners of the language to answer these, I think.
There's a reason a link to the language spec is included. :) (This is something that is emailed to people and they mail the answers back the next day. It's not a whiteboard exercise.)
