https://twitter.com/oe1cxw/status/1021768463277326337 … I don't want to participate for credit, but I'll DM you when ready (currently not ready. If it were a _C_ quiz though... :P)
We are helping a subcontractor hire a Verilog person (with a strong focus on Verilog language details and being able to work with the Verilog LRM). So I created a short Quiz for them to use. Anyone here brave enough to try it? My DMs are open.
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Thanks. Twitter will use this to make your timeline better. UndoUndo
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I'm in!
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I just looked at this, it's diabolical! I'm going to have to cosy up to the Verilog spec and dive into sign extension, x pessimism, and other dark corners of the language to answer these, I think.
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