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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Hackster.io‏ @Hacksterio 24 Aug 2018
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      Time for some FPGA fun with the @arduino MKR Vidor 4000!pic.twitter.com/uKaBST5pLu

      1 reply 28 retweets 109 likes
    2. kal9001‏ @kal9001 24 Aug 2018
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      Replying to @Hacksterio @arduino

      I'm planning on getting my hands on one of these - some day. Not a fan of the edge connector, or the pads on the underside though, think I would prefer this in a mega formfactor with all of the pins on both the FPGA and the SoC exposed on the headers.

      1 reply 0 retweets 0 likes
    3. 𝕬𝖑𝖊𝖝𝖆𝖓𝖉𝖗𝖊 𝕯𝖚𝖒𝖔𝖓𝖙‏ @adumont 28 Aug 2018
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      Replying to @kal9001 @Hacksterio

      IMO @arduino made a bad choice by sporting an Intel FPGA chip that doesn't have an open-source toolchain support (as opposed to some Lattice family FPGA which can be configured with #icestorm toolchain). CC @oe1cxw

      3 replies 3 retweets 8 likes
    4. Piotr Esden-Tempski @esden@chaos.social‏ @esden 28 Aug 2018
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      Replying to @adumont @oe1cxw and

      Even better question to ask is why @arduino did not invest into documenting the FPGA they chose, to make sure the chip they chose gets open tool support. Or are they only interested in OS for marketing purposes? I am sure they have the money to pay for that effort… ;-)

      1 reply 0 retweets 3 likes
    5. andrea‏ @be17068 28 Aug 2018
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      Replying to @esden @adumont and

      Indeed, this really is the mindset for turning this issue to the right way. We need @arduinoteam to be aware of #yosys and explain what good can come if they will be part of It!

      1 reply 0 retweets 2 likes
    6. 𝕬𝖑𝖊𝖝𝖆𝖓𝖉𝖗𝖊 𝕯𝖚𝖒𝖔𝖓𝖙‏ @adumont 29 Aug 2018
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      Replying to @be17068 @esden and

      #yosys but how could Arduino team document it, when it's Intel IP, it's not open AFAIK. Of course, it would be great if @intel were to contribute to #yosys. Hopefully that happen one day.

      1 reply 0 retweets 0 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 29 Aug 2018
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      Replying to @adumont @be17068 and

      We didn't need help from Lattice to document the ice40 or ecp5 bitstream. We didn't need help from Xilinx to document the 7-series bitstream. Why do you think the Arduino team couldn't document the bitstream of that Intel FPGA if they wanted?

      1:57 AM - 29 Aug 2018
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      • Piotr Esden-Tempski @esden@chaos.social Juan Gonzalez 𝕬𝖑𝖊𝖝𝖆𝖓𝖉𝖗𝖊 𝕯𝖚𝖒𝖔𝖓𝖙
      2 replies 0 retweets 4 likes
        1. 𝕬𝖑𝖊𝖝𝖆𝖓𝖉𝖗𝖊 𝕯𝖚𝖒𝖔𝖓𝖙‏ @adumont 29 Aug 2018
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          Replying to @oe1cxw @be17068 and

          good point 👌

          0 replies 0 retweets 2 likes
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        1. andrea‏ @be17068 29 Aug 2018
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          Replying to @oe1cxw @adumont and

          i too suppose @arduinoteam COULD do it or eventually could fund someone (like @symbiotic_eda or @ico_TC ) do it. but a tweet storm is about making them understand they SHOULD do it!

          2 replies 0 retweets 3 likes
        2. 𝕬𝖑𝖊𝖝𝖆𝖓𝖉𝖗𝖊 𝕯𝖚𝖒𝖔𝖓𝖙‏ @adumont 29 Aug 2018
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          Replying to @be17068 @oe1cxw and

          No doubts it can be done — technically, but will @Arduinoteam dare to reverse engineer 🔬@Intel IP to make it happen? 🤔 And would @intel let them?

          1 reply 0 retweets 1 like
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