Almost forget, it's time for another formal verification quiz! Will the design below pass?pic.twitter.com/EuxePAkLXV
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This would have been my answer, except ... I can't find $initstate defined anywhere in the System Verilog specification. Another answer would be to use |=>, but that requires the Verific enabled front end. f_past_valid works, although I agree its quite "hacky".
$initstate is a Yosys extension. generating your own f_past_valid is a good portable way of doing this.
