Thank you all for you kind words of support yesterday.
I'm very fortunate to have such a great community here. Thank you.

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Do you have pricing information somewhere ? Unfortunately I doubt I can convince my company to license it, as we are not doing a lot of HDL :(
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There will be various options. For evaluation purposes and occasional use there will be cloud instances with everything pre-installed for 10 USD/hr.
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Will there be free open source tools available to synthesise and verify VHDL locally?
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There is a VHDL frontend, I think this is the one https://github.com/forflo/yodl , which is not included because it's gpl'ed. Verification should work the same, since when you add an assert in verilog it lowers to https://github.com/YosysHQ/yosys/blob/master/techlibs/common/simlib.v#L1274 … which yosys should correctly convert to smt-lib2.
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