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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 21 Aug 2018
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      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩 Retweeted OSS FPGA & ASIC EDA tools

      One of our proposals was rejected because "the experts didn't understand in what way model checking is useful for hardware". Looks like they did not have this problem when evaluating other model-checking related proposals.https://twitter.com/ico_TC/status/1031848651314921473 …

      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩 added,

      OSS FPGA & ASIC EDA tools @ico_TC
      Stanford University will get 6 Mio USD to implement SW for Formal Verification of Verilog IP. They are going to use Yosys (which is luckily freely available and of so high quality that they can use it out of the box that they even do not need support of its author) pic.twitter.com/DQSPgpCnNE
      Show this thread
      8 replies 23 retweets 58 likes
      Show this thread
    2. Jose Renau‏ @jrenauardevol 22 Aug 2018
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      Replying to @oe1cxw

      You have to remember that one of the main reasons for darpa and nsf is to fund PhD students in topics with areas of interest. The big money is to pay students, at most 1 month summer salary for nsf.

      1 reply 0 retweets 1 like
    3. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 23 Aug 2018
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      Replying to @jrenauardevol

      I get that. But can't those students work on new stuff, not get funded to replicate features that are already available in the existing FOSS tools? Every box in this flow chart is something that Yosys+SymbiYosys can already do (and in a manner that I'd deem production-ready).

      1 reply 0 retweets 1 like
    4. Jose Renau‏ @jrenauardevol 23 Aug 2018
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      Replying to @oe1cxw

      They will to have papers, more likely they will reuse yosys, or in this case maybe just focus on chisel generated verilog. Phd Students can not graduate just with infrastructure, they will be forced to do something beyond this.

      1 reply 0 retweets 0 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 23 Aug 2018
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      Replying to @jrenauardevol

      DARPA is funding the implementation of the proposed work. The proposed work in this case seems to be re-implementing functionality that's already there in Yosys. (Yosys has RTLIL, they implement their CoreIR, Yosys has write_smt2 and yosys-smtbmc, they create their CoSA, etc.)

      7:57 AM - 23 Aug 2018
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      • Piotr Esden-Tempski @esden@chaos.social
      1 reply 0 retweets 1 like
        1. New conversation
        2. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 23 Aug 2018
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          Replying to @oe1cxw @jrenauardevol

          It may very well be that the student working on that has to do something beyond that to graduate. (That may or may not be part of DARPA funding. We don't know.) But that doesn't explain why DARPA is giving money to those unis to just re-implement existing Yosys functionality.

          1 reply 0 retweets 1 like
        3. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 23 Aug 2018
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          Replying to @oe1cxw @jrenauardevol

          If the focus is actually new research then I see no reason why they can't do that ontop of the existing infrastructure that we already provide. (Except that they probably can't charge DARPA 6 Mio USD if they can't claim they have to build everything from scratch.)

          0 replies 0 retweets 1 like
        4. End of conversation

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