Things I want for XMAS:
1) VHDL front-end for #Yosys.
2) Formal verification support for above.
3) Verilog netlist -> schematic generator.
4) Better OSS ASIC place & route with timing/clock-tree gen.
5) To get paid for making 1, 2, 3 or 4.
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I checked out QFlow once; it felt rather primitive. The main issue with KLayout (or any OSS layout tool) is that it lacks Cadence PCell support, which makes it almost useless for serious analog layout. Unfortunately, PCells are mostly distributed in encrypted form by fabs. :(
I have KLayout on my list of things to examine closer. Do you have any experiences with it that you can share, besides the missing PCells support?
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It's been a while since I used it and I know it's gotten better since then. Real-time design rule checking/hints is one of the things that was missing or just not good enough. Integration with existing PDKs is still missing, AFAIK.
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Other things needed, but not necessarily in KLayout: parasitic extraction tool with SPICE export, layout-vs-schematic (LVS) checker.
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