Newsletter Number Nine! https://internals.rust-lang.org/t/the-embedded-working-group-newsletter-9/8185 … - RISC-V bare metal support lands in @rustlang nightly, and an RFC to use @llvmorg's LLD as the default linker for `thumb*` targets!
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How much memory requires Rust on Risc-V 32?
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Replying to @ico_TC @rustembedded and
@dvc94ch would probably be better to answer this, but since this is "bare metal", it only requires as much memory as your code needs, there is no language runtime/overhead for memory.1 reply 0 retweets 1 like -
Replying to @bitshiftmask @ico_TC and
I think the real question here is "will it run on a picorv32?" and the answer is, I intend to find out soon...
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Replying to @dvc94ch @bitshiftmask and
I am so excited about this! A viable, rusty alternative to Microblaze would be amazing! Seems picorv32 is the most promising fpga capable riscv core at the moment?
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Replying to @marcschettke @bitshiftmask and
See https://github.com/riscv-rust/picosoc-example … for a blinky example to get you started
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Replying to @dvc94ch @marcschettke and
If we add one target for riscv softcores to rust, which one would you prefer? rv32imc or just rv32im?
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Replying to @dvc94ch @symbiotic_eda and
Here’s a data point: Coremark fits in the FE310’s 16 KB icache with C and runs really great. Without C it doesn’t fit and runs twice slower.
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Here is another set of data points. PicoRV32 on a LUT4 architecture without HW multiply: C adds +24% area, M adds + 21% area. (Both add +45% area. They share zero resources, as on would expect.) Or, since you already have M in the mix: rv32imc is +17% compared to rv32im.
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Pretty cheap. It wouldn’t take a very big program to get that back in code size savings.
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Replying to @BruceHoult @oe1cxw and
picorv32 supports the C extension and vexriscv has wip support for the C extension. Are there any other popular foss riscv softcores with a large userbase that don't support the C extension? Ideally at some point we'll also support rv32i and rv32im for educational cores.
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