@oe1cxw Hey, when you had questions on the Verilog spec, were there any resources (preferably w/ humans on the other end) that helped get you answers?
I can't really rely on yosys/simulators to give me all the answers.
Did you read the actual spec? Especially Verilog is reasonably short and easy to read. (SystemVerilog not so much :)
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No, I've only gone to the spec as-needed/read the sections I've needed. The spec does a good job explaining many things of course. But often, I'm left w/ questions about ambiguities/omitted information. Would be nice if the Verilog equivalent of http://esdiscuss.org existed.
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Part of my fear about "sitting down and reading the spec cover to cover" is that since later parts of the spec build upon earlier parts, I'll start having a large amount of questions about how things are worded depend on questions I had earlier- i.e. questions always cascade :D.
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I've been working with the SV spec for a couple of years now and I still manage to find new stuff in it every now and then. Latest one was 'assignment patterns' for structs/arrays. 1000 pages is a lot to cover...
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