Writing an FPGA IP core roughly analogous to std::unordered_set. This will be fun...
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I recently saw this in some expensive 3rd party IP. It's Verilog 101, I was shocked to find it.
Just to be clear: (1) Using <= and = in clocked blocks (mixing or not) is okay, if you follow a certain set of nontrivial rules for the use of = and do not mix for the same reg. (2) Using <= in a combinatorial block is practically always a bug (mixing or not doesn't matter).
