Is there any resource on 'reset' modeling in a #SystemVerilog testbench? Specifically, I'm interested in discussions about modeling reset as a 2-state/4-state variable.
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Is really x to 0 considered a negedge? Thought that required 1 to 0. I also remember that
@oe1cxw had some trick for transitions at time 0
Yes. X-> 0 ist a negedge. Imo there should be no clock transition at time zero in a clean sim test bench to avoid init-edge races.
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Aha. I probably assumed no negedge since falling_edge in VHDL doesn't trigger on x to 0. One of those subtle details :)
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IMO, whether X to 0 is considered a negative edge should be undefined. One shouldn't count on it being an edge, or on it not being an edge. (VHDL definition of falling_edge function notwithstanding.) Same for X to 1 regarding rising edge.
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