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I'll take a stab at figuring out this issue. I assume I need IEEE 1364-2005 and 1364.1-whatever_version_is_newest?
IEEE Std 1364.1-2002, or the 2005 draft standard (newer got finished). Unfortunately the IEEE 1364.1 standards never really exactly matched the "industry standard conventions" for Verilog synthesis, so you also need to know what the envelope of behaviors "found in the wild" are.
Well no standard in practice is actually implemented completely to spec. You can just yell at me if I get some behavior in practice wrong :P
I concluded the behavior I'm seeing is due to a //synthesis translate_off construct. It's a softcore; the simulation initializes r0 to 32'b0. First insn in my firmware is: xor r0, r0, r0. According to table 5-14 of 2005 spec, x ^ x = x, so no registers ever get initialized.
So about a dozen or so insns in, all the "x" values propogate to the outside world/bus in the post-synthesis simulation and everything goes to hell. Initializing r0 to 32'b0 using //synthesis translate_off prevents this. Doesn't solve my _real_ problem, but good to know.
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