@oe1cxw I found a post-synthesis-simulation mismatch in a design generated by yosys! Do I get a prize?
(More seriously, while I found this SO answer very helpful, https://stackoverflow.com/questions/45172834/how-to-run-post-synthesis-simulation-with-the-icestorm-ice40-fpga-flow … I'm not sure how to proceed; I can generate a mismatch with as little as "proc; flatten")
Depends. If Yosys should have produced an error then, yes, please create a minimal example. If it is a Synthesis Simulation mismatch that arises from the differences in Verilog synth and sim standards then there is nothing I can do. If you are unsure, create mcve I will tell you.
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I'll take a stab at figuring out this issue. I assume I need IEEE 1364-2005 and 1364.1-whatever_version_is_newest?
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IEEE Std 1364.1-2002, or the 2005 draft standard (newer got finished). Unfortunately the IEEE 1364.1 standards never really exactly matched the "industry standard conventions" for Verilog synthesis, so you also need to know what the envelope of behaviors "found in the wild" are.
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