mindblowingly cursed futurehttps://twitter.com/cynicalsecurity/status/1040611124784312321 …
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Replying to @bitemyapp
the x86 privilege model is materially more complex than the ARM equivalent and is much less amenable to formal verification, SMM code plays a crucial role in maintaining platform security properties and cannot be "stubbed out", you actually need to respond to SMIs because they
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Replying to @alt_kia @bitemyapp
get raised when code writes to certain control registers (and the SMM code *must countermand the writes*, rather than the CPU blocking the writes from the beginning), and SMM prot is a mess of complicated control regs rather than using MMU (like ARM TZ): https://www.blackhat.com/docs/us-15/materials/us-15-Domas-The-Memory-Sinkhole-Unleashing-An-x86-Design-Flaw-Allowing-Universal-Privilege-Escalation.pdf …
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Replying to @alt_kia @bitemyapp
it's not reflexive Intel-hating, it's that there's legit problems with platforms that require motherboard OEMs to ship correct SMM code (that needs to handle arbitrary input securely) to enforce properties that other architectures enforce with either MMU or a few lines of Verilog
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Replying to @alt_kia @bitemyapp
and simple verilog code ("only issue a write to a protected reg if privilege level is high enough") is far easier to verify against simple properties ("don't write to these control regs if you're not sufficiently privileged") than *all* the interworking components for the Intel-
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Replying to @alt_kia @bitemyapp
like scheme -- which forcibly involves stuff like "semantics of SMI interrupts", "memory model", "multi-core/multi-socket considerations", and of course "the correctness of Turing-complete code provided by your motherboard OEM written by bad C coders"
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this thread is like femdom except for cpu architectures
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