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  1. proslijedio/la je Tweet
    5. velj

    Bluespec, Inc. is delighted to open-source our compiler for the BSV/BH High-level Hardware Design Languages. Enjoy!

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  2. proslijedio/la je Tweet
    3. velj

    第1層 アーキテクチャレベル:軽い目まいと吐き気 第2層 ビヘイビアレベル:重い吐き気と頭痛、末端の痺れ 第3層 レジスタ転送レベル:平衡感覚の異常、幻覚や幻聴 第4層 ゲートレベル:全身に走る激痛と、穴という穴からの流血 第5層 トランジスタレベル:全感覚の喪失、意識混濁、自傷行為

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  3. proslijedio/la je Tweet
    31. sij

    . Andrew Feldmanさん (CEO, Co-Founder at Cerebras) のビデオが YouTube公開になってました (当初公開されていた vimeoは削除) 安田さんの記事と共にお勧めです! ※新しいワークフローは ANLとの共同研究から生まれている?

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  4. proslijedio/la je Tweet
    29. sij

    Listening to talk about improving Verilog generation in at the Chisel Community Conference.

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  5. proslijedio/la je Tweet
    29. sij

    [技術書典8 Day2 あ06]で新刊出します。Verilog&Chisel解説しながらCPU自作やEDK2で作るUEFIブートローダ解説、CTFやvimrcの話を(多分)一冊で!(人々が進捗生みすぎてしまったら二冊になります) |

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  6. proslijedio/la je Tweet
    29. sij

    Thank you to for the open sourcing of the Characterization Description Format on GitHub. !

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  7. proslijedio/la je Tweet
    24. sij
    Odgovor korisniku/ci
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  8. proslijedio/la je Tweet
    26. sij

    . Yann LeCunさんの EMC^2, NeurIPS 2019での Grand Keynoteです "What DL Hardware Will We Need", EMC^2 What will be the killer app of embedded DL hardware? Yes, obviously, Facebook is working on DL hardware for AR glasses と明言されてますね。

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  9. proslijedio/la je Tweet
    23. sij

    Google Dataset Search is now officially out of beta. "Dataset Search has indexed almost 25 million of these datasets, giving you a single place to search for datasets & find links to where the data is." Nice work, Natasha Noy and everyone else involved!

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  10. proslijedio/la je Tweet
    23. sij

    Yahoo! Final part of the "introduction to Formal Verification" series is now available on youtube:

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  11. proslijedio/la je Tweet

    "What do you mean you just wrote this new tool!? That's not how academia works! You first have to evaluate all the other tools, and show that writing a new tool is time and resources well spent, and then write it all down. Now go back and do all of that." - My BSc Thesis Advisor

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  12. proslijedio/la je Tweet
    20. sij

    . Pattersonさんは比較的早い時期から Google Pixel Visual Core開発の主要メンバーとして参加されていたようですね "Architecture for high performance, power efficient, programmable image processing" 2015-04-23: filed 2018-05-08: granted

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  13. proslijedio/la je Tweet
    19. sij
    Odgovor korisniku/ci

    => "Systems and methods for implementing chained tile operations", Intel, Patent Appl, Oct 3, 2019

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  14. proslijedio/la je Tweet
    17. sij
    Odgovor korisniku/ci

    => "Optimal Streaming Permutations and Transforms: Theory and Implementation", PhD Thesis, 2019 SGen Producing efficient HW designs operating on streaming datasets FFT, FPGA '18 Slides

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  15. proslijedio/la je Tweet
    19. sij

    . DARPA ISAT Study Group (外部識者) による報告です Interfaces to Unlock the Specialized HardwarE Revolution, Apr 2019 RISC-V等 Open HWにも関係しますね。 Co-designed Stack例として Spatial、TVM、Stream Dataflow Execution

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  16. proslijedio/la je Tweet
    19. sij
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  17. proslijedio/la je Tweet
    8. sij
    Odgovor korisniku/ci

    => "The Story of SPARC Architecutre (The Design and Development of SPARC)", Wayne Rosing and David Patterson, University Video Communications, Jul 19, 1989, MP4 SPARC project 14 people 5: Gate Array 2: CPU board 5: Language & OS

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  18. proslijedio/la je Tweet
    13. sij

    . UC Berkeley Architecture Research (ラスト Asanovic教授) による RISC-V向け Systolic Array acceleratorです An Agile Systolic Array Generator Enabling Systematic Evaluations of DL architecture, arXiv, Dec 7, 2019 色々な構成で検証

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  19. proslijedio/la je Tweet
    12. sij

    Verilator 4.026 was released yesterday. I added support for the SVA implication operator |-> over the holidays. I hope to carve out enough time to make ABV viable with Verilator at the end of 2020. What do you miss the most?

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  20. 10. sij

    Patterson氏がChiselの存在に触れて くれた。😊

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