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Broadly. So for a 10 GHz clock and a 2cm die, the propagation delay (ctr to edge) becomes ~1/3 of a clock cycle... Add in rise time distortions and it's a serious issue.
I see. Thinking aloud: omitting constants, you want L f << c, where L is the linear dimension of the chip, and f is the clock frequency. If the characteristic size of elements on the chip is d (more or less the feature size), and you want N elements, you have N d^2 = L^2...
... so the constraint on clock frequency is f << c / [d sqrt(N)]. Pretty interesting constraint.
"Constraint" isn't really the right word, of course. Something more like "obstacle" is better - you need clever strategies to deal with the drift. I'm sure it can be done, but it'd be a pain.
There are other considerations like how the rc time constant for shrinking metal line dimensions eats into available clock cycles but yeah it's a totally interesting constraint...
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