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The skew actually comes from propagation velocities! Clock distribution networks need to be aware and phase shift the clock for synch operation.
Interesting. I guess that makes sense - if the signal is propagating say ~3 millimeters (?) even at ~lightspeed it's going to take 1/100 of a nanosecond. At 3 GhZ, that's 1/33rd of a clock cycle. Am I understanding the issue correctly?
Broadly. So for a 10 GHz clock and a 2cm die, the propagation delay (ctr to edge) becomes ~1/3 of a clock cycle... Add in rise time distortions and it's a serious issue.
I see. Thinking aloud: omitting constants, you want L f << c, where L is the linear dimension of the chip, and f is the clock frequency. If the characteristic size of elements on the chip is d (more or less the feature size), and you want N elements, you have N d^2 = L^2...
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