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We had a huge effort on this at DARPA. A key consideration is clock skew across the device as speeds increase. You end up with "clock domains" that shrink, large overhead in mitigating skew, and what effectively becomes a multicore architecture for fixed die size
Interesting! What causes the skew / how do you resync or mitigate it?
The skew actually comes from propagation velocities! Clock distribution networks need to be aware and phase shift the clock for synch operation.
Interesting. I guess that makes sense - if the signal is propagating say ~3 millimeters (?) even at ~lightspeed it's going to take 1/100 of a nanosecond. At 3 GhZ, that's 1/33rd of a clock cycle. Am I understanding the issue correctly?
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