Incentive to commit more $$ to R&D From 2013 on demand economics -> https://www.cnet.com/news/end-of-moores-law-its-not-just-about-physics/ … 2015 on costs of r&d -> https://arstechnica.com/gadgets/2015/02/intel-forges-ahead-to-10nm-will-move-away-from-silicon-at-7nm/ … 2017 tech for forging ahead -> https://spectrum.ieee.org/semiconductors/nanotechnology/euv-lithography-finally-ready-for-chip-manufacturing … All these aggregated by/courtesy of Don Greenberg @ Cornell http://www.graphics.cornell.edu/academic/nbay6120/ …
Anyone know why Intel’s chip fabrication process got so stuck at 14 nanometers?
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Ben Thompson (stratechery) dove into this a bit and then also linked a good Twitter thread I'll try to find
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https://stratechery.com/2018/intel-and-the-danger-of-integration/ … and the next daily post The Twitter thread:https://mobile.twitter.com/stevesi/status/1011284522179031040 …
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Because we have been patterning 65, 45, 32, 22, 14 nm features with 193 nm light. Double, triple, etc patterning has its limits. Photoresists have sensitivity and granularity limits. 13.5 nm (EUV) is not a panacea. This article is still relevant: https://spectrum.ieee.org/semiconductors/design/seeing-double …
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But TSMC got there
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Heisenberg should know
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Please clarify your question. What do you mean by 'got so stuck at'?
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They announced they'd be at 10nm years ago, and they're still not mass-producing.
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It's tough to decide what nanometer has gotta go.
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