Day 9 part A solution! No regexes ;-) @mendel
It could probably be shorter...
https://github.com/lisa/adventofcode/blob/dd33ea26948ad0bddd1fbeb17b34dbaf23c9edb6/2017/day09.go …
This reminded me of some Verilog I wrote a long time ago for a serial port. (https://gist.github.com/lisa/971336 )
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Just finished part A! Now for part B ;-)
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Holy crap what happened in part B??!
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