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that is exactly what I want to do, yes
That should be interesting. Can you actually fine trim the frequency finely enough for that to work? (without just resampling the output data host side). I thought you were actually going to send a ref clock, which would be more robust.
good question. I wouldn't know until I try--and that's why sending a reference clock is a fallback. I like synchronization because it's much simpler, all boards have the same role, as opposed to leader/follower with clock distribution
the SYNC pin is open-drain only (I ran out of push-pull pins), but the driver is pretty strong, so distributing a 10 MHz clock (fmin of the PLL) is a fallback option in case what I want doesn't work out
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