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did you know that DDR4 timings are intimately dependent on temperature (there is a temperature probe inside the modules). for example, the hotter the RAM is, the faster it gets refreshed by the controllerpic.twitter.com/4KpjIwsHTz
Not just that, it also needs periodic runtime retraining. Which on Tegra210 is done... by the Linux kernel, because they were too lazy to implement it on the BPMP CPU. Guess which feature isn't upstreamed yet, totally killing performance since the RAM runs at safe boot timings?
Also, there's apparently so much voodoo in DDR4 initial training that even Google couldn't get Nvidia to open source it. It's the *only* part of the Pixel C boot chain that isn't open source. It's implemented by a blob the bootloader embeds and calls into.
Huh... that's very bizarre...
The rpi does it in the VC4 every 500ms. It actually causes a stall visible to userland, so there's a bootloader option to turn it off (disable_pvt).
Looks like they sped it up and got rid of it. The Tegra actually has a rather complicated process (since it all runs on code from RAM, it can't actually disable RAM) to stage the frequency changes and then run them on a hardware sequencer.https://github.com/raspberrypi/firmware/issues/640 …
What does this sort of runtime retraining on #OpenPOWER? The OCC?
@stewartsmith, @RaptorEng, @adi_gangidi do any of you know?
No idea. I'd guess it's in the memory controller? It's not in OPAL or Linux at least.
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