Repeat after me: glitching works. Every time. If you don't have power, reset, and clock monitoring, your chip *will* be pwned. No exceptions.https://twitter.com/bernfroe/status/959405824840957952 …
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Glitch detection is not a simple thing, especially on voltage rails. Clock glitch detection means you're sacrificing 10-20% of performance because you have to close timing at a higher frequency. Reset glitch monitoring is fairly trivial (synchronize/buffer the input).
I wonder if you can do risk analysis on clock glitching to optimize performance. Say, if your critical path is in the vector unit, maybe you don't care as long as you guarantee the OS never uses vector ops. Or you only care about an OOB secure processor, not main CPU.
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Of course metastability can bite you in the ass but... You know, from a "convince the higher ups something is better than nothing" perspective.
Thanks. Twitter will use this to make your timeline better. UndoUndo
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