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The difference is that RAM doesn't wear out, so nobody cares that it works this way. The RAM can also combine a long sequence of reads or writes, sequential or scattered, within one page, into one read, a sequence of I/Os, and a write back to the array. (3/n)
So next time someone tells you "RAM can be accessed at a granularity of one bit", remember that's not really true. It actually uses huge pages just like Flash, which is fundamental when memory is organized as a big 2D array (the page size is one dimension). (4/4)
Addendum: I meant 64 kibibits (64 Kibits or 64Kib) in my original tweet, not 64 kibibytes. It's usually something like 8 bits per chip × 8 chips = 64 bits for a whole DIMM, and pages (rows) are 1024 addresses within each bank, so 65536 bits.
Even SRAM and similar tend to be addressed in at best "lowest addressable unit" of CPU, not bits.
True, externally they can usually be addressed at best bytewise (wider SRAM usually has byte enables). However, SRAM reads are not destructive, so they *do* qualify as bit-addressable at the array level (given appropriate column select mux). But you pay for that with 6T/bit.
The other thing to consider is that these page reads/writes have gotten maybe 2-3x faster in the last 20 years All the perf improvements have come from them getting bigger & being able to stream data out of them faster
Yup! The fastest DDR4 only has half the latency of 100MHz SDRAM from 20 years ago. I/O has just gotten wider and faster and we started pumping out two bits per cycle.
Do they teach Cray XMP memory architecture in CS degrees these days? And the design of data structures to speed memory access of vectors. Wonder how much of that is still relevant.
Agreeing about 1bit access, that's never been true for me going back to 1970s. Mask, shift, or, xor --on MF CPUs was the only way to touch a single bit.
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