On first glance it looks like many CPUs are vulnerable to same-privilege mis-speculation leaks (e.g. in JIT engines - disable eBPF jit if you have it enabled), but Intel has the real SNAFU in letting it leak across privilege modes.
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Looks like it is. "Intel has also started releasing microcode updates that basically add some chicken bits and also let you flush branch predictor state to handle the context switch case." https://lkml.org/lkml/2018/1/3/859 …
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But apparently it's horribly slow on existing CPUs, due to restrictions on what they can do in microcode. Newer ones will come with a performant IBRS instruction to invalidate branch prediction state.
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Considering branch prediction & speculative loading is very likely on the hot path, I don’t think it’s implemented in microcode :/
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But if the problem is branch predictor injection, they can just flush branch predictor state on kernel/userspace transitions. That likely wouldn't have a massive performance impact.
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The branch one is described as affecting ARM and AMD, if I’m reading right?
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It doesn't seem to be clear to what extent. It's heavily uarch specific and the research seems to have focused on Intel.
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