Brainstorming an open FPGA breakout/devboard design with lots (>100) of I/O and USB. I should start writing a design doc soon...
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That's what I use, but take care that ENIG is not good enough for the slave PCB. Hard gold is almost mandatory for slot and it's not cheap
Depends on # of insertions I guess? The idea is the slaves can be "disposable". People got away with tinned edge conns in the ISA days...
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Yep, but ENIG-plated slots starts to fade after 15-20 insertions only :-/
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Could be acceptable for some of the use cases... Experimentation needed I guess. Considering this is mostly for hacks, not "long term".
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Seems PCIe connectors use more pressure in much smaller area than good ol' ISA slots. So more friction and signal integrity issues.
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Ah, interesting. I'll look into it. Makes sense I guess, with the signal integrity requirements.
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