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marcan42's profile
Hector Martin
Hector Martin
Hector Martin
@marcan42

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Hector Martin

@marcan42

If it ain't broke, I'll fix it! I'm porting Linux to Apple Silicon Macs at @AsahiLinux. http://patreon.com/marcan  | http://github.com/sponsors/marcan 

Tokyo, Japan
marcan.st
Joined May 2009

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    1. hikari, Kanbaru enthusiast  🌟 other Andrea‏ @hikari_no_yume 13 Jun 2017
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      silly projects I would implement if I had the know-how: PCIe-over-USB

      2 replies 0 retweets 2 likes
    2. hikari, Kanbaru enthusiast  🌟 other Andrea‏ @hikari_no_yume 13 Jun 2017
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      Replying to @hikari_no_yume

      USB doesn't provide DMA, I believe? But why should that stop me.

      4 replies 0 retweets 0 likes
    3. whitequark‏ @whitequark 13 Jun 2017
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      Replying to @hikari_no_yume

      you can't do PCIe over USB because the former needs a hard worst-case latency guarantee and the latter explicitly avoids one

      1 reply 1 retweet 3 likes
    4. Ridley @ a safe distance‏ @11rcombs 13 Jun 2017
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      Replying to @whitequark @hikari_no_yume

      Wait, PCIe has latency guarantees? Didn't @marcan42 tunnel PCIe over some crazy-slow setup for PS4 stuff and have it work fine?

      2 replies 0 retweets 1 like
    5. whitequark‏ @whitequark 13 Jun 2017
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      Replying to @11rcombs @hikari_no_yume @marcan42

      I believe yes, see PCIe Base Specification 3.5.2.1 and Table 3-4

      1 reply 0 retweets 0 likes
    6. whitequark‏ @whitequark 13 Jun 2017
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      Replying to @whitequark @11rcombs and

      I'm sure you could work around that if you can control the entire system, like by gating the TLP Transmitter's clock

      1 reply 0 retweets 1 like
    7. hikari, Kanbaru enthusiast  🌟 other Andrea‏ @hikari_no_yume 13 Jun 2017
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      Replying to @whitequark @11rcombs @marcan42

      ahahaha

      1 reply 0 retweets 0 likes
    8. whitequark‏ @whitequark 13 Jun 2017
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      Replying to @hikari_no_yume @11rcombs @marcan42

      or maaaaybe by terminating PCIe on either end and then using flow control to effectively stall the transmitter? no idea about PS4

      1 reply 0 retweets 0 likes
    9. Hector Martin‏ @marcan42 13 Jun 2017
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      Replying to @whitequark @hikari_no_yume @11rcombs

      You do not tunnel the data link layer. Those timeouts are for TLP transmission acks, not TLP to completion (which is what we care about).

      1 reply 0 retweets 2 likes
      Hector Martin‏ @marcan42 13 Jun 2017
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      Replying to @marcan42 @whitequark and

      For comparison, USB has tight reply ACK timing requirements too (but nobody who isn't writing a USB device controller has to deal with that)

      10:23 PM - 13 Jun 2017
      • 2 Likes
      • hikari, Kanbaru enthusiast 🌟 other Andrea Jevin Sweval
      2 replies 0 retweets 2 likes
        1. New conversation
        1. Hector Martin‏ @marcan42 13 Jun 2017
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          Replying to @marcan42 @whitequark and

          For PCIe, the section you want to look at is 2.8. Note how it doesn't say much. Table 7-25 has the actual values. >10ms is recommended (!)

          1 reply 0 retweets 2 likes
        2. whitequark‏ @whitequark 14 Jun 2017
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          Replying to @marcan42 @hikari_no_yume @11rcombs

          thanks!

          0 replies 0 retweets 1 like
          3. End of conversation
        2. New conversation
        1. Erin  ✨ 💽‏ @erincandescent 14 Jun 2017
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          Replying to @marcan42 @whitequark and

          Really tight! Incidentally, this is part of where the cable length limits come in. You're running into light speed (in copper) delays!

          1 reply 0 retweets 2 likes
        2. Hector Martin‏ @marcan42 14 Jun 2017
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          Replying to @erincandescent @oshepherd and

          Yup. I once ran into this due to @xmos's crappy half-software UDC. Its API has critical undocumented timing constraints.

          1 reply 0 retweets 1 like
        3. Show replies

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