@marcan42 To make sure you notice it doesn't work soon and connect it to a proper reset source.
Xilinx ISE, I hate you so much. Why on earth would you default an unconnected PLL RST signal to 1 (i.e. dead)?!?!?!?
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@doragasu Doc says "The PLL automatically locks after power on, no extra reset is required". Does NOT say RST should be tied to 0 if unused. - Show replies
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@marcan42 somehow this totally fails to surprise me. Ah, Xilinx ISE.Thanks. Twitter will use this to make your timeline better. UndoUndo
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