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Hector Martin (@marcan@treehouse.systems)

Myth: Apple chips have magic x86 translation. They don't. Myth: Apple chips are the only ones to implement the x86 TSO memory model. Nvidia Denver/Carmel and Fujitsu A64fx do too. Myth: Apple chips have proprietary x86 emu related-features. FEAT_AFP is in ARMv8.7.

6:04 AM · Jun 7, 2022Twitter Web App

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Hector Martin (@marcan@treehouse.systems)

@marcan42

Jun 7

Replying to

@marcan42

I'm not actually aware of any Rosetta-related features that aren't TSO nor already in ARMv8.7. Let me know if you know of any. I don't think any non-Apple ARM chips implement *both* of those *today*, but nothing's stopping them, it's not magic Apple secret sauce.

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Hector Martin (@marcan@treehouse.systems)

@marcan42

Jun 7

(Nit: Apple's version of what FEAT_AFP does is proprietary because it predates the official spec, but it does the same thing, just with vendor-specific registers instead. Apple also have other pre-release ARM features implemented like that, like parts of FEAT_ECV.)

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Hector Martin (@marcan@treehouse.systems)

@marcan42

Jun 7

Also both TSO and FEAT_AFP are relatively minor things and probably 90% of x86 software will run fine on ARM translation even if you ignore both of those problems. The Windows emulator does that.

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Hector Martin (@marcan@treehouse.systems)

@marcan42

Jun 7

For completeness:

@dougallj

did find one sneaky Apple-only feature, the parity flag bit. It's optional though, and Rosetta will run without it.

@never_released

also just tested Rosetta 2 on non-Apple hardware and it runs fine.

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Dougall

@dougallj

Jun 7

Replying to @marcan42

Hmm - it looks like they get the parity flag by using "MRS Xn, NZCV" and then reading it from (Xn & 0x4000000)... I didn't know about FEAT_AFP - is this a standard thing too?