As much as I like verilog, it’s so easy to fuck up something that’s not immediately obvious. This is amazing for giving the power of HDLs to a non-HDL audiencehttps://twitter.com/marcan42/status/1343785608666259457 …
You still need to know how HDL works when you write the actual applet code, but we take care of all the boilerplate, and nMigen provides tons of useful abstractions to avoid common gotchas. So it lets you build *useful* things even if you're not very experienced.
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Also, there's the built in logic analyzer. You can just pull full traces of FIFO in/out data, pin state, and arbitrary internal signals. With integrated throttling (for synchronous applets) to guarantee no buffer overflows.https://github.com/GlasgowEmbedded/glasgow/issues/65 …
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That’s pretty neat
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I’m sure it would help with the most common mistakes I make though. It’s always a stupid inferred latch somewhere because I’m terrible at boilerplate
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Yeah, the nMigen programming model is *deliberately* designed around modern synchronous logic, so it stops you from shooting yourself in the foot in many of those ways.
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Disclaimer: I *love* glasgow. However, I found it non-trivial to get started; partially this is the "fault" of the wonderfully engineered, well-abstracted/layered sample plugins. "Just adding a simple thing" turns into reading a lot of code to understanding the framework.
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This is in strong contrast to an under-engineered framework like Arduino - as much as I dislike Arduino, you're maximum of 2 layers apart from assembly, and everything is easily hackable. With glasgow, everything is hackable also but only after understanding the custom framework.
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