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It's designed to make it very, *very* easy to build bespoke applets to do whatever you want, which means you can easily use it as stands today even if it doesn't support what you need... But that means I also expect upstream features to grow much faster in the future!
This is the power of just-in-time FPGA synthesis and reconfigurability. There is no limit to how many features you can have. There is no special coordination needed to switch between them. Just write another applet.
The freedom to make the bitstream *specific to a single invocation* also means you don't need to deal with configuration *at all*. Your bitstream can be tailored to how many bits the user needs on a port. An internal word size. Anything. It's just python.
No multiplexers. No selectors. No complex routing logic. You just write python. Need a configurable number of bits? Just use a python variable called `bits` in your code. You don't even have to think about it. And no routing logic means it performs better too.
Really, the whole thing is just so friction-free it's silly. All the scaffolding is done for you, you just write code There is a *very* minor learning curve to the framework, but the basic example applet is just 71 lines of code you can just copy and paste and edit.pic.twitter.com/lXqJt3Jitv
Notice how ~none of that is HDL (it's the empty first class that does nothing). The second class just tells Glasgow what you need for your applet, like a list of pin names (which become command line options for the user to specify the pin mapping).
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