btw something that's increasingly obvious as I dissect this pile of VLIW-looking instructions: two decades ago, a GUI could accelerate its rendering on something like Rage128 or its pre-TeraScale successors, by uploading custom microcode with its common register write sequences
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the thing that confirmed my suspicions and let me know a few things, like how the register offsets are encoded (shifted right by 2, makes sense, they're all 32-bit anyway) was this: the MPEG_INDEX handler in R520_cp.bin packet docs: http://developer.amd.com/wordpress/media/2013/10/R5xx_Acceleration_v1.5.pdf#page=54 … register bonanza!pic.twitter.com/SaepbxhcSJ
The way I started reversing this was that I immediately saw register offsets (>>2, but that's a common code convention for AMD too) in the hex dump, so I knew those were load/stores. Then run one- or two-opcode firmwares and use that as data in/out.
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I wasted a lot of time because I didn't know the >>2 thing, and they're like 11 bits, so e.g. in "3d bc", the >>2 register offset is actually "05 bc", i.e. 0x16f0 also I don't even own a Rage128, the closest thing I have is an R300-ish in an AMD HP SFF desktop circa 2006 D:
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and it's, like, integrated in the chipset and I don't know how weird it is compared to cards, and I wanted to start at Rage128 anyway speaking of, Rage128 cards are cheap, but... they're all AGP, and the oldest PC I have (the aforementioned HP SFF desktop) only has PCIe and PCI
End of conversation
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