so it's like TTA
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lmao good thing I googled around, looks like GCN's "microcode format" has already been reverse engineered (I swear I saw it in a talk, too!), and r1/r2's descriptions perfectly match what I can see in as far back as Rage128 https://github.com/fail0verflow/radeon-tools/tree/master/f32 … (*waves at
@marcan42*)
Ha. So they've been doing this since Rage128, but with weirdo VLIW style cores? Geez, I'm glad I got the sane(ish) RISC design!
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the thing that confirmed my suspicions and let me know a few things, like how the register offsets are encoded (shifted right by 2, makes sense, they're all 32-bit anyway) was this: the MPEG_INDEX handler in R520_cp.bin packet docs: http://developer.amd.com/wordpress/media/2013/10/R5xx_Acceleration_v1.5.pdf#page=54 … register bonanza!pic.twitter.com/SaepbxhcSJ
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The way I started reversing this was that I immediately saw register offsets (>>2, but that's a common code convention for AMD too) in the hex dump, so I knew those were load/stores. Then run one- or two-opcode firmwares and use that as data in/out.
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