If there's a lesson I learned with Glasgow, it's that transparent bidirectional level shifters of any kind are evil.
revA/B are broken for that reason (e.g. the I²C applet will never work), and revC0 pull-up support was broken because we used I²C-specific ones internally. 
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"Why is my I²C bus self-oscillating at 3MHz‽" (oh yeah and it's unrecoverable) Second lesson was that voltage regulators are 1-bit DRAM chips with ~1-2 minute data retention when powered off.
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Replying to @marcan42
That was why I designed such a complex I/O cell for CLARKE (formerly STARSHIPRAIDER). I actually used two different unidirectional output buffers depending on VCCIO, and a comparator for the input. More expensive, but far more flexible than one magic chip.
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Replying to @azonenberg @marcan42
I put the project on ice ~2 years ago because of my house renovation and not having a fast enough scope to adequately debug it. Maybe I can get back to it soonish.
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Replying to @azonenberg
Well, you went full crazy spec for yours :-) Glasgow is happy with bidirectional shifters *with direction input*. The reason revA/B didn't use those was to save FPGA pins to avoid having to use a BGA chip...
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Replying to @marcan42 @azonenberg
OTOH, since revE will be modular, we can have *all of* dumb unidirectional or slow-config-directional "gimme twice the I/Os" modules, revC style bidir I/O modules at 2 FPGA pins per I/O, and crazy CLARKE style do it all frontends :)
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Replying to @marcan42
Yeah the CLARKE frontend design is 4 pins per channel: LVCMOS33 output + enable, then LVDS input. Each 8-bit IO card also gets I2C control and power. It will eventually synthesize VCCIO on board but I never got that far.
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Yeah, similar to the plan for revE; I²C everywhere and power and I/Os. I assume you won't mind if we design it so that we can just drop in your I/O cell design too :-)
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Replying to @marcan42
I would love to. Need to finish that I/O cell though. Maybe I'll get back to it in 2021... glscopeclient and probe stuff has been eating a lot of my time.
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