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Well, you went full crazy spec for yours :-) Glasgow is happy with bidirectional shifters *with direction input*. The reason revA/B didn't use those was to save FPGA pins to avoid having to use a BGA chip...
OTOH, since revE will be modular, we can have *all of* dumb unidirectional or slow-config-directional "gimme twice the I/Os" modules, revC style bidir I/O modules at 2 FPGA pins per I/O, and crazy CLARKE style do it all frontends :)
Yeah the CLARKE frontend design is 4 pins per channel: LVCMOS33 output + enable, then LVDS input. Each 8-bit IO card also gets I2C control and power. It will eventually synthesize VCCIO on board but I never got that far.
Yeah, similar to the plan for revE; I²C everywhere and power and I/Os. I assume you won't mind if we design it so that we can just drop in your I/O cell design too :-)
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